Defining 3D Technologies May20 By Webmaster • Posted in Industry News May 20, 2014 The Knowledge Portal on 3D InCites features a number of informational posts, including this useful discussion of 3D and 2.5D technologies and terminologies. (The embedded video is also quite good.) See also this list … [Read More]
More on the Tezzaron/Fermilab collaboration May15 By Webmaster • Posted in Industry News May 15, 2014 This is the new 2D prototype of Fermilab’s VIPRAM chip. The final version is to be built in 3D. See article “A chip off the new board” [here].
A powerful argument for 3D memory May8 By Webmaster • Posted in Industry News May 8, 2014 How much of an SoC’s area is consumed by memory? Semiconductor Engineering’s Brian Bailey reports: “Today it is closer to 50% to 55%. We have seen a few cases where it is more than 85% of the chip area. The trend line is up and to the right.” “It is more expensive … [Read More]
Invitation to Join the 3D Community May8 By Webmaster • Posted in Industry News May 8, 2014 Yesterday Francoise von Trapp published an enthusiastic and well-documented Open Letter to the chip design community: “It is my pleasure to inform you that the waiting time is over, and 3D ICs are ready to implement.” Read the … [Read More]
Temporary Bond / DeBond – Why Bother? Apr30 By Webmaster • Posted in Tezzaron in the News April 30, 2014 “What we need is an approach that eliminates temporary bond/debond and allows scaling of the wafer thickness.” — Sitaram Arkalgud, as quoted by F. von Trapp, who reports that Surya Bhattacharya agreed with this assessment during the 3D IC Forum at SEMICON … [Read More]