DiRAM4™ 3D Memory

Our flagship project is DiRAM4™, the 4th generation in a series of dis-integrated high performance memory subsystems.

DiRAM4™ is our first heterogeneous logic-process plus DRAM-process prototype. It utilizes a high performance logic process to implement unusually high performance amplifiers, drivers and decoders while at the same time, a genuine low-leakage DRAM process is used to render the bit cell array. High voltage interface circuits are implemented on third thick-oxide logic process best suited to fabrication of I/O cells.

Family NamePortsBanks
DiRAM4-64C64™64640.6 – 1.3V
64 Gb8 Tb/s9 ns
DiRAM4-64C32™64640.6 – 1.3V
32 Gb8 Tb/s9 ns
DiRAM4-64C16™64640.6 – 1.3V
16 Gb8 Tb/s9 ns

DiRAM4 incorporates Bi-STAR® test and repair technology which allows wafer and die-level test and repair…and it keeps on working throughout the life of the die, even after it is installed in the field.

DiRAM4™ can be fabricated in multiple density configurations: 64Gigabit (8GigaByte), 32Gb (4GB), and 16Gb (2GB). Reducing density does not reduce performance.

Heterogeneous transistor-level 3D allows devices to be fabricated with DisIntegrated 3D techniques, like DiRAM4™. Among other advantages a chip designer can realize using these techniques, modular designs can become a reality. For example a device can be customized with new I/O layers. Alternate I/O layers can be used to convert a device to any number of interface standards, including SerDes, Pico-SerDes (Ultra Short Reach SerDes), and even Optical I/O – but the popular I/O option is most likely to be a very wide low voltage CMOS I/O interface. The DiRAM4-64Cxx, for example,  has CMOS I/O device has 64 ports, each port having a separate I/O 32 bit data bus that can be operated in either Burst-of-2 or Burst-of-8 mode. Each port is completely independent, with its own clock, control, and address inputs as well as 32 data in and 32 data out connections. The HSTL-like interface is extremely flexible and can be powered with a nominal VDDQ anywhere from 0.6V to 1.3V. The input buffer trip point is controlled by VREF, normally set to VDDQ/2.

More information is available under NDA. Contact us to learn more: info@tezzaron.com