Our Technology 101

We do not believe 3D is a packaging technology … we believe it is an architecture enabler.

our-technologyAt Tezzaron we use a radically different manufacturing flow to enable a radically different device architecture.

Our primary focus has been on 3D memory for a very simple reason. A RAM is a very regular device that is a perfect candidate for process development. Our flagship device is our 4th generation 3D memory subsystem, designated DiRAM4™. We recognized years ago that traditional economics of semiconductor process development were becoming unmanageable and that the processes themselves were becoming more and more fragmented and specialized. Both of these primary trends are working against the industry’s fundamental desire to bring more functionality into a single package. The most glaring example has been DRAM. The specialized process used to build DRAM bits is simply awful when it comes to building high speed logic circuits. Conversely, building DRAM bits with high performance logic processes (eDRAM) has proven very difficult and expensive…the memory bits themselves are large and leaky. As the industry demands higher and higher performance memory with more and more logical capability, matters have gotten really out of hand. What may be even worse is that due to these same problems, commodity DRAM products devote remarkably little of their die space to actual storage anymore. The problem is only getting worse as time goes on. So Tezzaron has elected to go a different direction.

At Tezzaron we build our devices in many layers on many wafers, so we can use the right wafer process for each job. We use a high performance CMOS process to build high performance logic circuits like sense amps, write drivers, and decoders. We use a DRAM process to build memory storage bits. We use cheaper, larger feature-size processes when they offer the right capabilities at a good cost, and we reserve expensive advanced processes for when they are needed. We use that mix of processes to build a single, highly optimized device. Given the industry demand for complex SOC products and the relentless trend towards process specialization as we try to continue lithographic shrinks, we believe a heterogeneous stacking approach is critical to industry progress.

DiRAM™ is our product name for “Dis-integrated Random Access Memory.” Every other vendor in history has built memory devices on a single wafer, but Tezzaron separates (dis-integrates) the elements of a memory device in order to build them on separate wafers. Some wafers contain mostly bit cells; others contain mostly high-speed logic circuits, etc. The bit layers are stacked onto a logic layer (the “controller”) that contains sense amps, write drivers, address decoders, and other elements that read and write the memory bits. Under all that we attach another logic layer (the “I/O layer”) that translates the signals from the controller into whatever voltage and protocol is needed by off-chip devices (processor, FPGA, optical link, etc.).

The DiRAM™ architecture is made possible by Tezzaron’s manufacturing methodologyUsing the dis-integrated architecture allows unprecedented density, speed, and power reduction, all of which would be either outright impossible or absurdly expensive any other way.

The DiRAM™ architecture is made possible by Tezzaron’s manufacturing methodology. As you might suspect, when you elect to build elements of a device on multiple layers, it follows that the device in question does not become functional until the elements are joined; that is, until the layers are stacked. That means that the elements are essentially untestable before stacking. Or to put it another way, the DiRAM™ architecture requires that we stack untested die.

The most common responses to that are “That’s impossible,” “That will never work,” and “That’s crazy.” We understand your confusion.

Tezzaron does indeed stack untested die. More accurately, Tezzaron stacks entire wafers. If you are going to stack entire wafers, it doesn’t help to know which die are good and which are bad. All of the die are going to get stacked. Moreover, assuming there are good die mixed with bad on each wafer, there will be no way to prevent good ones from stacking onto bad ones. Each stack of die is made with the die that happens to live at the same address on each wafer. By now, if you were thinking we are crazy, you are probably sure of it. But we have a trick or two. Before you write us off completely, keep in mind that “virgin yield” for any modern memory product is roughly zero and even logic products use post-fabrication test and repair techniques; which is to say that from a practical point of view there is no such thing as a “good” die, if  “good” means “does not need to be repaired.”

Our competitors’ 3D assembly techniques depend on copper Through Silicon Vias (TSVs) to provide the vertical interconnect through their stacks. Copper is used because it is one of the few metals that will fill a 50 to 100 micron deep hole that is 5 to 10 microns wide at the top. Keep in mind, the via diameter is a key factor when it comes to the number of vertical wires that run through a stack of dies. Smaller wire diameter leaves room for more wires. But via aspect ratio, the ratio of via depth to via diameter, usually ends up at about 10:1. The result is that wafer thickness is key to vertical interconnect density.

The metal normally used for contacts in most modern CMOS process flows is tungsten. But tungsten steadfastly refuses to go down even a 50 micron deep hole that has a reasonably small diameter. 5 to 10 microns deep is fine, but 50 microns is out of reach. You can’t make a good TSV with tungsten if your wafers are 50 microns thick. So why not make the wafers thinner? Because they are fragile and often break. Even if they don’t break, if they get too thin and too flexible, the silicon crystal matrix breaks down and the transistors stop working properly. Not good. So if you want a wafer that you can handle safely, and probe test to find the good dies before you singulate them, you are stuck with having a fairly thick wafer and pretty deep TSVs…and stuck with filling the holes with copper. But there is another way. If you are willing to bond two wafers together first, and then thin just one of them, the thick backing wafer provides the structural integrity to allow very aggressive thinning of the companion wafer. And it follows that if you have two pairs (each having one thick and one thin wafer), they can be bonded thin-to-thin, and that allows one of the thick outer wafers in that four wafer stack to be thinned. Now you have three very thin wafers, each less than 20 microns thick, bonded to one thick backing wafer. The process can be repeated over and over until the stack contains a remarkable number of layers. The key point is that because we have radically thin wafers, we can use tungsten to fill vias. And even with a 10:1 aspect ratio limit, with a wafer thickness of 20 microns or less, vias can have diameters of 1 micron or less.  Radically thin wafers are the biggest part of the secret to Tezzaron’s having more than 100 times the vertical interconnect density of our competitors. It is easy to see why we say we do “via-free wafer stacking.” We simply don’t use the large copper structures most folks are talking about when they use the term “TSV” when we build our 3D memory. We use tungsten contacts; big ones to be sure, but essentially contacts. We call them SuperContacts™.


Thin wafers are key to the story, but there is more. Virtually every conventional CMOS process flow includes tungsten metallization, including tungsten contacts, because tungsten is an almost ideal metal for use on silicon wafers. That is in large part because it is thermally compatible with silicon. Tungsten expands and contracts are about the same rate as silicon, so it does not cause too much physical distress on the silicon. Tungsten contacts are well understood and have scaled well across many generations of process technology. As a result, tungsten contacts are cheap and reliable, and because they are very small they have almost negligible inductance, capacitance, and resistance. As mentioned before, tungsten can easily fill a 10 micron deep hole with a 10:1 aspect ratio, but it is also true that SuperContacts 1 micron wide (or less) can be arrayed on a sub-3 micron pitch (the center to center distance between repeated objects). Compare that to what can be achieved with 50 micron thick wafers and 5 micron wide TSVs. Copper TSVs are being placed on a 40 to 50 micron pitch. Copper is thermally incompatible with silicon. Copper expands and contracts more than silicon as temperature changes. If there is too much copper going through a wafer, a normal temperature change can break the wafer. Even if the die or wafer does not break, if a transistor is located too close to a copper TSV, the expansion or contraction of the copper can change the operating characteristics of the transistor, perhaps throwing the device in question out of spec or making it non-functional. As you may have guessed, that is not the case with tungsten. Tungsten is very nearly perfectly thermally compatible with silicon. So while 5 micron wide copper TSVs may need to be spaced on a grid of 40 or more microns per step, tungsten SuperContacts can be organized on a pitch that is about two times the SuperContact diameter, (e.g. 0.6 micron wide SuperContacts can be on a 1.2 micron pitch, and 1 micron wide SuperContacts can be on a 2 micron pitch.)  So not only can SuperContacts be made with very small diameters, they can also be arrayed on a very tight pitch. The net result is radically more vertical interconnect per unit area across the surface of each die and therefore through the 3D stack.

Because we have vastly more vertical interconnect through our stack than any other vendor, we can do potent and comprehensive post-assembly repair. As mentioned earlier, die almost invariably contain faults. Vendors build redundant structures into their products and invoke those redundant circuits as needed during the manufacturing / test process, turning “bad” dies into “good” devices for sale. What makes Tezzaron different is that we have much finer-grained repair. And we are not limited to repairing bad bits. We have a variety of redundant circuit elements available, and we even have spare SuperContacts. Moreover, because we have so much vertical interconnect and because the layers are so intimately connected with each other, we can use redundant elements from one die to repair defects in another die in the stack. The net effect is the most powerful repair architecture in the industry … and the only approach that solves the fundamental problem with 3D.

The most basic problem with conventional 3D is that each additional die in the stack lowers the net yield of the stack. Because burn-in and test occur after die stacking, and because one bad die in the stack can “break” the whole stack, taking an ordinary approach to manufacturing guarantees that stacking can only make things worse. But at Tezzaron, stacking adds repairability. Adding more dies to the stack can actually make the stack more reparable. At Tezzaron, 3D makes things better – which, if you are doing 3D products, is the way to go.

ourtech-stackheightAt Tezzaron we call our built-in self-test and repair architecture Bi-STAR®. Most ICs implement at least some rudimentary form of built-in self-test.Not many do built-in self-test and built-in repair. Despite this, almost everyone relies on very expensive and relatively slow Automatic Test Equipment (ATE), which has been the standard approach for over 40 years. Unfortunately, the performance of DiRAM4™ completely overwhelms the capabilities of any ATE from any test equipment vendor anywhere in the world. But Tezzaron needed to do post-assembly test and repair anyway. So it was natural for Tezzaron to leverage its earlier self-test technology into a complete production-class test suite. The result, Bi-STAR®, lets us deliver fully tested bare die (un-packaged high performance memory subsystems). “Fully tested” is a significant issue. It means that un-packaged DiRAM4 stacks are burned-in and speed tested for full speed operation. That is a very rare thing in the 3D world. The bonus is that Bi-STAR testing is faster, cheaper, and more thorough than can possibly be managed by external ATE.

The crazy innovation that makes Bi-STAR® work is that each stack includes a built-in ARM™ microcontroller that manages the stack. In the case of DiRAM4, there are 256 hardware test sequencers, right inside the stack. When this dedicated test hardware is coupled with the distributed redundant circuit elements available for repair, highly effective built-in test and repair become a reality.

So there you have it. The fundamental decision to bond untested wafers allows us to produce the world’s thinnest wafers. Because we have crazy thin wafers we can use tiny tungsten SuperContacts rather than huge copper TSVs for vertical interconnect. Because we have tiny, almost electrically invisible vertical interconnect, we can put connections exactly where they are needed and we have enough of them to do thorough post-assembly repair. Because we have Bi-STAR test and repair, it is possible for an increasing the layer count in a stack to produce a yield enhancement rather than a detriment.

We are able to bond untested wafers successfully. The result is a transistor-level 3D dis-integrated IC technology that has the most aggressive combination of density, performance, and low power ever created. That seems like a worthwhile endeavor to us.