At Tezzaron we believe that calling 3D a “packaging technique” is like calling the internet a new way to send telegrams. We view 3D as a fundamentally new structure for integrated circuits. Previously, a device’s functionality had to be shoe-horned onto a single die. Not any more! Instead, we spread the device’s elements across multiple die, sorting the elements by type. This “dis-integration” lets us build each die using the optimal process technology for its elements. We then stack the highly optimized die to reassemble a single “dis-integrated” circuit. Our new dis-integrated 3D circuits deliver higher performance, lower cost, and much higher value than could ever be achieved with conventional 2D integration or with conventional die stacking.
In the past, you could reliably improve electronics by shrinking the transistors. Smaller transistors made everything faster, cheaper, and more power efficient. Those days are gone. Transistor shrinking may continue for a time, but making them cheaper has become very problematic. And the up-front costs of a new IC development project has gone out of reach for all but very few companies.The traditional approach to improving integrated circuits has entered an era of aggressively diminishing returns.
Nonetheless, there is an urgent drive for better, faster, cheaper electronics, fueled by today’s wildly popular electronic gadgets. The elements in these new circuits really push the limits. Their characteristics are radically disparate, demanding highly specialized processing techniques. And wafer processes are indeed increasingly more specialized – each is optimized for one particular type of element, and not well suited to other types at all. This disconnect is troublesome for the entire industry. The usual solution is to apply a patchwork of compromises around the disparate elements. Tezzaron has a better way.
Tezzaron neutralizes the entire problem by dis-integrating the design and building different elements on different wafers using different processes. Memory bits and access transistors, for example, can be built in a process highly optimized for those elements. Amplifiers, decoders, and write drivers can be built on another wafer, using a process optimized specifically for them. The external interface layer can be yet another wafer. This makes the 3D layers modular – as interchangeable as the bits in a power drill – each built in the best process for the task at hand.
This “dis-integrated” architecture delivers unrivaled performance on every measurable metric: higher density, lower power and higher bandwidth. Tezzaron goes far beyond simply developing a technique for designing new memory. We have developed a family of processes, techniques and know-how that will enable an entire ecosystem for the development of high performance devices that both we and our partners can use to create products with unprecedented performance at very reasonable cost.