The Tezzblog

A powerful argument for 3D memory

How much of an SoC’s area is consumed by memory?  Semiconductor Engineering’s Brian Bailey reports:

“Today it is closer to 50% to 55%. We have seen a few cases where it is more than 85% of the chip area. The trend line is up and to the right.”

“It is more expensive to move information than compute it. Off-chip and off-package is two orders of magnitude greater than the cost of storing a bit. Finding ways to move data more efficiently is paramount.”

Moving that memory in-package appears to be the best hope to reduce the transfer power. “3D IC is being driven by power consumption and then secondarily form factor. While they are more expensive to manufacture today, the costs will catch up.”

Read the article in Semiconductor Engineering.