Invitation to Join the 3D Community May8 By Webmaster • Posted in Industry News May 8, 2014 Yesterday Francoise von Trapp published an enthusiastic and well-documented Open Letter to the chip design community: “It is my pleasure to inform you that the waiting time is over, and 3D ICs are ready to implement.” Read the … [Read More]
Temporary Bond / DeBond – Why Bother? Apr30 By Webmaster • Posted in Tezzaron in the News April 30, 2014 “What we need is an approach that eliminates temporary bond/debond and allows scaling of the wafer thickness.” — Sitaram Arkalgud, as quoted by F. von Trapp, who reports that Surya Bhattacharya agreed with this assessment during the 3D IC Forum at SEMICON … [Read More]
3D InCites covers the ITRS Roadmap Apr23 By Webmaster • Posted in Industry News April 23, 2014 “At the beginning of April, the Semiconductor Industry Association released the 2013 International Roadmap for Semiconductors (ITRS) … the combination of 3D device architecture and low power devices will usher in a new era of scaling identified in short as ‘3D Power Scaling.’ … all roads … [Read More]
Semiconductor Engineering’s Mark LaPedus cites Tezzaron and Novati Apr17 By David Chapman • Posted in Tezzaron in the News April 17, 2014 “Chipmakers are reaching various and challenging inflection points. In logic, many IC makers face a daunting transition from planar transistors at 20nm to finFETs at 14nm. And on another front, the industry is nearing the memory bandwidth wall. So perhaps it’s time to look at new alternatives.” [Read More]
Tezzaron at the GSA Silicon Summit Apr10 By Webmaster • Posted in Tezzaron in the News April 10, 2014 “At the GSA Silicon Summit this afternoon there was a discussion of 3D IC and 2.5D IC. The session was moderated by Javier DeLaCruz of eSilicon and the panelists were: Calvin Cheung of ASE (an OSAT) Gil Lvey of OptimalTest (a test house) Bob Patti of Tezzaron (semiconductor company specializing in TSV-based designs) Riko … [Read More]