Tezzaron in the News

Tezzaron’s first working 3D memory chip – a memory stack with through-silicon vertical interconnect – appeared in 2004. Since then our memory stacks have grown continually more sophisticated, with hugely increased capacity. Finally, at the GSA 3D IC Packaging Working Group meeting (July 23), … [Read More]

“What we need is an approach that eliminates temporary bond/debond and allows scaling of the wafer thickness.” — Sitaram Arkalgud, as quoted by F. von Trapp, who reports that Surya Bhattacharya agreed with this assessment during the 3D IC Forum at SEMICON … [Read More]

“Chipmakers are reaching various and challenging inflection points. In logic, many IC makers face a daunting transition from planar transistors at 20nm to finFETs at 14nm. And on another front, the industry is nearing the memory bandwidth wall. So perhaps it’s time to look at new alternatives.” [Read More]

“At the GSA Silicon Summit this afternoon there was a discussion of 3D IC and 2.5D IC. The session was moderated by Javier DeLaCruz of eSilicon and the panelists were:

Calvin Cheung of ASE (an OSAT)
Gil Lvey of OptimalTest (a test house)
Bob Patti of Tezzaron (semiconductor company specializing in TSV-based designs)
Riko … [Read More]