Soft Errors in Electronic Memory Jan31 By Webmaster • Posted in Documents January 31, 2004 A Tezzaron white paper. Download PDF: Soft Errors in Electronic Memory
Tezzaron/Tachyon in the News: 2001-2003 Dec31 By Webmaster • Posted in Tezzaron in the News December 31, 2003 November 2003: Semiconductor Investment and the Future (Gilder Technology Report) (see “Consequences” near the bottom of page 3.) November 2003: New memory technology promises top speeds (Electronic Products) September 2003: Wafers Stack on Copper Super-Vias (SolidState Technology) August 2003: Tezzaron delivers challenge to SRAM, DRAM (EE Times) August … [Read More]
New Memory Technology is World’s Fastest Aug18 By Webmaster • Posted in Press Releases August 18, 2003 Naperville, IL – August 18, 2003 Tezzaron Semiconductor today announced a prototype memory device with record-breaking speed: 1.3 nanosecond (ns) latency, 1 ns cycle time, and a throughput of 2 Gigabits/sec on each pin. The underlying technology for this device is a patented 3-transistor cell that senses changes in electrical current … [Read More]
Another Giant Step Toward 3-D Silicon Jun29 By Webmaster • Posted in Press Releases June 29, 2003 Vertical interconnects are tiny, precise, abundant A set of multi-wafer stacks – the first ever built with vertical through-silicon connections – demonstrates the electrical connectivity needed for tightly integrated 3-D semiconductor chips. The wafer stacks were created by Tezzaron Semiconductor using proprietary processes developed by that company. Before being bonded into … [Read More]
DRAM Pricing Sep15 By Webmaster • Posted in Documents September 15, 2002 A Tezzaron white paper View pdf document: DRAM Pricing