The Tezzblog

Economics create a mandate for vertical packaging according to Ed Sperling of Semiconductor Engineering.  Read his article here.

Francoise von Trapp – “The Queen of 3D” – wonders why more companies aren’t designing 3D chips with through-silicon interconnect.  Her conclusion: “it all comes down to courage. We’ll see who has it and who doesn’t”!

Read her article … [Read More]

Mark LaPedus of Semiconductor Engineering published an interesting discussion about the push for smaller and smaller ICs, driven mostly by the mobile device market.  Read his article here.

Semiconductor Engineering on June 26 published two articles about exciting (if unsettling) shake-ups in our industry:

Ed Sperling says too many choices and uncertainty turn new chip architectures into riskier gambles—and force a rethinking of what’s next.  Read here.

Brian Bailey says industry is mixed over … [Read More]

Experts See Tougher Memory Choices
An interesting discussion in Semiconductor Engineering highlights the importance of choosing the right memory – and the right memory vendor.  Brian Bailey reported on June 12 from DAC, where the conversation included Herbert Gebhart (Rambus), Bernard Murphy (Atrenta), Patrick Soheili (IP Solutions and eSilicon), and John … [Read More]