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Tezzaron’s Response to Intel’s Tri-Gate “3D” Transistor

By Webmaster • Posted in Opinion

May 29, 2011

Intel’s new transistor is an impressive piece of technology – even more so because it is built in an extremely advanced 22nm process.  However, calling this transistor “3D” has caused some understandable confusion between these transistors and our 3D-ICs (or 3D chips).

Transistors are to a chip what bricks are to a house: if Tezzaron builds excellent 3D houses, then Intel has developed an excellent new brick.  Each layer of our 3D chips contains millions of transistors.  No matter what kind of transistors are used, Tezzaron’s FaStack® process can stack them in layers to create a 3D-IC with greater speed, lower power consumption, and a smaller footprint than could be otherwise achieved.

It would be an intriguing exercise to build a FaStack 3D-IC using Intel’s 3D transistors; there is likely to be a powerful synergy between the advantages offered by the two technologies.  Until such a project is proposed, Tezzaron will watch with interest – and with a tip of the hat to Intel.

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Additional Information
On May 4, 2011, Intel announced “3D” transistors developed in the 22nm process node. It’s unfortunate that Intel chose to use the term “3D,” causing even more confusion in an already confused 3D terminology landscape.

Reading the Intel press release carefully, one can see that Intel is announcing, not a 3D-IC, but a “Tri-Gate 3D transistor.” This appears to be a variation on the FinFET, a technology already widely known. The vertical “fin” of the transistor is the only 3D element of the design.

The difference between 3D transistors and 3D-ICs is not like the difference between apples and oranges, but more like the difference between apples and bicycles. Intel’s further shrinkage in process geometry to 22nm ahead of everyone else, despite their use of the term “3D,” is arguably just a traditional extension of Moore’s law.

Taken by itself, building transistors of any kind in a 22nm geometry is newsworthy, but it does not intrude on Tezzaron’s space at all. Our FaStack stacking technology can be used with wafers of any process node to achieve high density vertical interconnect in true 3D integration.

Intel’s new transistors undoubtedly offer benefits.  However, we can stack wafers containing any type of transistor to gain the additional benefits of multi-layered, fully integrated devices. As with other recent innovative breakthroughs, its is good to remember that, if they can build it on a 2D wafer, we can stack it into a 3D-IC — and that 3D-IC will offer advantages of density, power, performance, and reliability far beyond anything that can be achieved in a single-wafer, 2D device architecture.

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