The Tezzblog

July 27, 2017

The title of this post is stolen from an article by Ed Sperling, published in Semiconductor Engineering, July 20, 2017. I reference it here to cite it as recommended reading.

The list of problems with semiconductor processes beyond 10nm seem overwhelming. New nodes have always looked difficult to achieve, but I believe there is a growing consensus that this time, it’s different. We are in new territory.

What is striking to me about Ed’s article is not the litany of problems he identifies, but that the solutions he cites do not address the major issue; improving transistor density while also improving performance, lowering power and reducing costs, which has been the backbone of the success of the semiconductor industry for more than 60 years.

“Another option is to build chips with a number of different compute elements developed at different nodes.”

Ed does at least brush past the answer. The line quoted above is on the right track but then Ed heads off on a rabbit trail, talking about packaging technology, rather than semiconductor technology. Heterogeneous 3D is the right answer, but it must be implemented at transistor scale, not package scale, and that is Tezzaron’s focus. The end of the conventional approach to advancing the ball in the semiconductor industry has arrived. Who will partner with Tezzaron to take the lead in the next phase?