3D transistors, 3D chips, and 2.5D Apr9 By Webmaster • Posted in Tezzaron in the News April 9, 2014 “From the ultra-small 3D transistors described in papers at this month’s International Electron Devices Meeting (IEDM) in Washington, D.C., to the 2.5D and 3D multichip structures described at the 3D Architectures for Semiconductor Integration and Packaging (ASIP) conference held in Burlingame, Calif., designers are finding more ways to pack more … [Read More]
Tezzaron CTO Bob Patti at IMAPS Mar31 By Webmaster • Posted in Tezzaron in the News March 31, 2014 “The annual IMAPS Device Packaging Conference in Ft. McDowell, AZ is always a source for the latest packaging information … Bob Patti addressed the interposer cost issue head on during a panel session” read the article in Solid State Technology
News Items: March 2014 Mar31 By Webmaster • Posted in Tezzaron in the News March 31, 2014 In addition to other posts, Tezzaron is mentioned in two industry publications this month: GloFo Shows Progress in 3D Stacks (EE Times) IFTLE 183 RTI ASIP: Tezzaron… (Insights from the Leading Edge)
Advanced Packaging Alphabet Soup Creates Chaos for IMAPS 3D Panel Mar18 By Webmaster • Posted in Tezzaron in the News March 18, 2014 All hell broke loose at the 3D Panel discussion at the 2014 IMAPS International Device Packaging Conference. Nobody was hurt, and nothing got thrown, mind you, but it’s clear that we’ve got some very different opinions regarding one of my pet peeves – the ever-expanding and increasingly complex advanced … [Read More]
Tezzaron’s 3D Chips at the Instrumentation Frontier Mar11 By Webmaster • Posted in Tezzaron in the News March 11, 2014 “Fermilab organized an international consortium of a dozen physics laboratories to produce a demonstration 3D pixel-readout chip. They chose Tezzaron Semiconductor, a leader in the 3D field, as an industrial partner … Together, the laboratory consortium overcame design and manufacturing challenges to develop a highly successful 3D chip.” [Read More]