The 8-bit “Super-8051” microcontroller is 3D integrated with a layer of SRAM and runs at clock speeds up to 200 MHz. It executes all ASM51 instructions and uses the same instruction set as the 8031. Its Reduced Instruction Set Computer (RISC) core executes many of its instructions in a single clock cycle, providing a significant speed advantage over traditional 8051 devices that execute one instruction every twelve clock cycles. It also features extended 32-bit capabilities including an IEEE 754-compliant floating-point coprocessor with comparator, a multiply/divide unit, a population counter, and a leading-zero counter.
This fully functional 3D-IC prototype has been demonstrated at conferences around the world since its creation in 2004. Tezzaron’s patented FaStack® wafer stacking technology was used to bond and integrate the high-speed SRAM layer onto the processor layer, creating an extremely wide I/O bus. The successful creation of this revolutionary 3D-IC confirmed the potential of FaStack technology for new generations of cutting-edge devices.
To showcase its speed advantage over standard 2D chips, the “Super-8051” was run in a split-screen demonstration.
The “Super-8051” prototype features:
Up to 90% power reduction
Industry standard 8051 / 8031 software compatible
RISC architecture with up to x12 speed advantage / MHz over traditional 8051 family devices
Clock speeds up to 200 MHz
128KBytes of on-chip high-speed SRAM memory
IEEE 754-compliant floating point coprocessor for full arithmetic capabilities – up to 100 MFlops
Extended 32-bit computing functions including population counter, leading zero counter, and floating-point comparator
Dual data pointers for fast data block moves
Up to 200 MIPS and 100 MFlops
Full 8051-compatible architecture including:
The processor is supported by Keil® Software.
For more about Keil® software, visit their website.