At Tezzaron we believe that calling 3D a “packaging technique” is like calling the internet a new way to send telegrams. We view 3D as a fundamentally new structure for integrated circuits. Previously, a device’s functionality had to be shoe-horned onto a single die. Not any more! Instead, we spread the device’s elements across multiple dies, sorting the elements by type. This “dis-integration” lets us build each die using the optimal process technology for its elements. We then stack the highly optimized dies to reassemble a single – but extraordinary – circuit. Our new dis-integrated 3D circuits deliver higher performance, lower cost, and much higher value than could ever be achieved with conventional 2D integration or with package-on-package stacking.
In the past, you could reliably improve electronics by shrinking the transistors. Smaller transistors made everything faster, cheaper, and more powerful. Those days are gone. Transistors are now so small, shrinking them further produces very little improvement (if any); the field has entered an era of aggressively diminishing returns.
Nonetheless, there is an urgent drive for better, faster, cheaper electronics, fueled by today’s wildly popular electronic gadgets. The elements in these new circuits really push the limits. Their characteristics are radically disparate, demanding highly specialized processing techniques. And wafer processes are indeed increasingly more specialized – each is optimized for one particular type of element, and not well suited to other types at all. This disconnect is troublesome for the entire industry – but especially for building semiconductor memory. The usual solution is to apply a patchwork of compromises around the disparate elements. Tezzaron has a better way.
Tezzaron neutralizes the entire problem by dis-integrating the memory and building different elements on different wafers using different processes. Memory bits and access transistors are built in a process highly optimized for those elements. Amplifiers, decoders, and write drivers are built on another wafer, using a process optimized specifically for them. The external interface layer is on yet another wafer. This makes the 3D layers modular – as interchangeable as the bits in a power drill – each built in the best process for the task at hand.
This “dis-integrated” memory architecture delivers unrivalled performance on every measurable metric: higher density, lower power, higher bandwidth, and unbelievably higher transaction rate. Tezzaron goes far beyond simply delivering memory. We have developed an entire ecosystem of high performance memory infrastructure devices so that our customers can create memory subsystems with unprecedented performance.
Initially targeting the exascale supercomputing market, our Ayrees™ memory subsystem components include hubs, switches, photonic interfaces, and cooling blocks that can be combined to address the biggest scientific problems ever contemplated by humanity. When Tezzaron services are added to this suite of products, we can achieve feats heretofore as far out of reach as a web video call in an 1895 telegraph office. And these achievements become not only possible, but practical.