If you’re not already a semiconductor guru, our technology might seem like one more bit of gobbledygook in a sea of technical black magic. But it’s a fascinating story, and we think it’s worth explaining! So here’s the Tezzaron® story in simple terms:
Computer chips have been made exactly the same way for over 40 years. You start with a blank slice of silicon. You put down gossamer-thin layers of patterned metal and glass. Repeating this process in various ways creates transistors – lots of transistors – and tiny wires between them. Transistors and wires; that’s really all it takes to produce memory devices, microprocessors, amplifiers, and all those other chips inside your electronic gadgets.
A computer circuit board with chips
On the inside, each chip’s transistors and wires make up a single “integrated circuit” or IC.
Integrated circuits aren’t made one at a time; they’re made in big batches on circular silicon “wafers.” Each wafer is actually a single crystal of silicon, but that’s another story. Suffice it to say that dozens, hundreds, even thousands of integrated circuits are patterned on each wafer.
One wafer patterned with many integrated circuits
The wafer is cut up – “diced” – into individual integrated circuits. The rectangle of silicon containing one integrated circuit is called a “die” — or, alternatively, a “chip.”
A die (chip) with one integrated circuit
Each die is then packaged to protect the fragile silicon. The outside of the package is studded with metal connectors – pins or bumps – that let the die communicate with the rest of the world.
Two different chips, one packaged with pins and one with bumps
When all is said and done, some chips just don’t come out right. Silicon wafers often have subtle flaws that wreak havoc with the transistors. There’s also the chance of errors during processing, or microscopic bits of dust, or impurities in the materials.
Before the wafer is even diced it generally undergoes “probe testing” to see which die are good and which are bad (see the picture at the top of this article). Bad die are marked and discarded after dicing. However, the probe test can’t fully exercise all the functions of the chips; that can only happen after they’re packaged. Then they undergo some seriously tough testing. They’re even loaded into ovens and cooked!
A furnace used for chip burn-in
Only the strong survive this “burn-in.” The survivors go on to final test; they are connected to computers that thoroughly analyze their performance. The chips that fail are repaired or discarded; those that pass all the tests are sold to customers.
As technology has advanced over the years, the transistors and wires have gotten smaller and smaller. At the same time, more and more stuff has been crammed onto each chip. That’s why our devices – phones, for example – have gotten so small and powerful. But the bad news has been that despite transistors getting smaller, die have been getting bigger…lots bigger. And to add injury to that insult, today the biggest cause of power consumption and delay in modern ICs is the on-die wiring. Electricity flies through those wires are almost the speed of light…and it just cannot get much faster, no matter how great the transistors may be. Wire is wire. So that covers the delay problem. The other problem is that wires have resistance…they resist the flow of electricity. Not much but some and that results in heating. Not only that, they have capacitance. This is a tricky concept. Think of it this way… Each wire is a dead battery. To get the electricity to go from one place to the next the first thing that must happen is that the electricity must charge the battery. As soon as it is charged, the electricity is free to continue its trip to the far end of the wire. Sounds crazy, right? But that is the way every wire in the world works. It happens so fast when you plug in a toaster or turn on a flashlight that you cannot detect it happening, but it is…at close to the speed of light. The difference here is that modern ICs work at almost the speed of light so that charging delay is very noticeable. Not only that, it costs power. Every time the signal on the wire changes, the battery gets charged (or discharged) again and it is never 100% efficient. Some of the energy is converted to some other form…mostly to waste heat. That’s why your cell phone gets hot when you use it.
So the industry has two big problems. It is getting far harder and incredibly more expensive to make transistors smaller and wires are not getting more cooperative. In fact, as die continue to get larger because we want our chips to do more stuff, the wires just keep getting longer and longer. Tezzaron believes the industry has spent too much time focused on the X and Y directions on the face of the die. Tezzaron believes it is time to put some effort into the Z direction. Up.
Instead of making the transistors smaller, another way to get more of them into each chip is to stack several layers of circuitry into a package. These stacked circuits are called “3D-ICs” (three-dimensional integrated circuits).
There are many interesting ways to stack 3D-ICs, but they all have some things in common:
You can stack die on die, die on wafers, wafers on wafers, or a combination of these. You can put the layers together using adhesives, or melted metal, or covalent silicon bonds, or whatever works for you.
A silicon wafer starts out thinner than a dime, but you can’t stack a bunch of dimes and expect them to fit into a chip package. Somewhere along the line, the layers have to get thinner. You can thin a wafer before or after dicing; you can thin a die before or after stacking; but however you do it, you have to end up with a slim stack of circuits.
The layers of the stack need to communicate with one another electronically. They need some vertical wires – along the outside of the stack, or through the whole stack, or just between pairs of layers; a few big fat wires or a vast forest of tiny wires; one way or another, the circuits need to pass signals up and down. You can build wires into each layer before stacking, or drill holes for them after stacking; you can make them out of copper, aluminum, tungsten, polysilicon – any material that conducts electricity.
This is the really tricky part. One bad circuit can ruin the whole stack. Because the layers can’t be fully tested until they’re in a package, there is no way to know ahead of time whether all of them are good. The more layers in each stack, the higher the odds of having a bad one in there. Throwing out a lot of bad chips is expensive! If only a few chips make it through testing, they’re going to be awfully expensive chips. Solving this problem is obviously a high priority.
Most companies working in 3D are stacking die. Stacking die is great compared to stacking packaged parts, which has been done as well for quite a few years now. However, Tezzaron uses a radically different approach. We stack whole wafers. We stack whole wafers because doing so allows us to install far more (far smaller) vertical wires that carry power and signals up and down through the stack. Stacking wafers is what requires Tezzaron to take a new approach to everything else about IC design and manufacturing. Our suite of Di3D technologies, techniques and know-how are all brought to bear at once, in support of each other. We practice wafer-level stacking with hybrid bonding, tungsten interconnects, and built-in self-test and repair. Here’s a quick walk through the actual fabrication process.
Tezzaron stacks complete wafers, before they are cut into individual die. That’s wafer-level stacking. We don’t even probe-test the wafers first. It is only after all the wafers are stacked that we do any testing. And we agree, if our chips were designed in a conventional way, almost none of them would be any good. But our 3D stacked chips are not conventional. We have a few little tricks.
First of all, we stack the wafers without any adhesives. We use the silicon itself for the bond and minuscule bits of melted copper for electrical connections. That’s called hybrid bonding. The bond is actually stronger than the silicon itself – you can’t break the bond without breaking the wafers – and the connection is very, very thin.
At Tezzaron and everywhere else, the way to thin a wafer is to put it on a big flat turntable and grind it down. The circuits are on the top of the wafer, so normally, the wafer is put onto the turntable face up and the blank backside is ground away.
You have to be careful not to grind the wafer too far; when it gets thinner than a playing card it starts to become flimsy and can eventually crumble to dust.
But at Tezzaron we bond two wafers together first, face-to-face, and we put the entire two-wafer stack into the grinder. Because the bond is so strong, we can thin the top wafer until it’s just a film – thinner, even, than some germs. We can do that because the bottom wafer is still at full thickness, and it’s holding everything together. We can then bond another wafer onto the stack, face down, and thin it. And so on.
We bond each wafer before thinning, and the bond is strong enough that we can grind our wafers extraordinarily thin – about 1/10 the thickness of our competitors’ wafers. That’s our first little trick.
We make our vertical wires by drilling holes in the wafer and filling the holes with tungsten. There is a limit to how narrow and how long anyone can make wires like that. With today’s processing techniques, the length can’t be more than about ten times the width. Because Tezzaron’s wafers are so thin, the wires that run vertically through the wafer are quite short. And because they are so short, they can be very skinny.
Wafer cross-section showing a vertical wire
Our wafers are 1/10 as thick as those of the die stacking folks, so our wires are 1/10 as long, and they can therefore be 1/10 as wide. You would think that means we can put in 100 times as many vertical wires through the wafers (ten times more going across the wafer (horizontally in the X direction) and ten times more the other way (vertically in the Y direction). But we actually have far more than that because we use tungsten for our vertical wires rather than copper (like everybody else).
Although the industry uses copper for interconnect metal on wafers all the time, it turns out that copper and silicon are not very compatible with each other. It is one thing to put a layer of it on top of a die but it is quite a different thing to drive a copper nail through a die. (Each of these big copper nails is called a Through Silicon Via, or TSV.) One of the big incompatibilities is the rate at which copper and silicon expand when they get hot. Copper expands faster and more as it gets hot. As a result it puts pressure on the sides of the hole going through the wafer…and that is bad. Some pressure is OK, as long as there are no transistors nearby. If there are, and the silicon into which they are made gets stressed, those transistors can start acting differently…differently enough to disrupt the operation of the circuit in which the transistor is connected. And if the pressure gets great enough the wafer can actually break. Not good. The result is that the spacing between copper TSVs is controlled by the stress problem, not the physical size of the hole through the wafer. And worse still, because they can disrupt transistor functions, there are lots of places in the die where they cannot be placed. The result is that Tezzaron gets far more than 100 times more vertical interconnects through our stacks.
So why does anyone use copper? Why doesn’t everyone use tungsten? Because copper will go down a deep hole in a wafer and tungsten will not. But because our wafers are so thin, we can use tungsten.
So let’s recap. We bond wafers so that we can grind them very thin. We grind them very thin so that we can use tungsten to make out vertical wires. Because we use tungsten we can have FAR more vertical wires through our stack than folks who stack die instead of wafers. Why?
Radically dense vertical interconnect is what allows us to do DisIntegrated circuit design. Our tiny tungsten wires (we call them SuperContacts®) allow us to pass signals up and down through the stack every few transistors (e.g. from one flip-flop to another one on a different die), not just between major circuit elements (e.g. between a microprocessor and a RAM). We describe this approach as transistor-level 3D and the way we architect the chips we design, as dis-integrated circuit design, or Di3D™.
But all these vertical wires allow us to do one more critical step. Post-stacking test and repair.
Strange as it may seem, the chances are good that you may have never seen an electronic gadget that has 100% good chips inside, even when the device was brand new. It is very, very difficult to make an absolutely perfect chip. As a result, standard procedure in the IC business is to design chips with spare circuits in them. Then, after the chip is made, each die can be tested and in many cases, defective circuits in the die can be disconnected (using tiny fuses or other devices) and replacement circuits from the pile of spares on that same die that can be switched in to take over. If the defects are so bad there are not enough spares to do the job, or they are not located close enough to connect, or if there simply are no spares for the circuit that failed, the die is bad and goes in the trash. Because the biggest problem in ordinary 2D IC design is finding places to put the wires that connect the circuits on the die to each other. So the limited interconnect between spares and bad circuit elements is the biggest barrier to doing effective repair.
In any event, if the die can be repaired, the fix gets done and the repaired die go on to further testing and packaging. In the case of folks doing die stacking, those repaired die are the ones used to build the stack. And now you can see the big issue with wafer stacking. When wafer stacking, two whole wafer get bonded to each other. There is no way to not use some of the die. And if a bad die gets bonded to a good one, it is hard to see how the resulting pair will become good. But there is a way. We call it BiSTAR® for Built-in Test and Repair.
A two-layer die (with nickel for scale)
Because we have billions of SuperContacts at our disposal, we can include lots of spares and put them everywhere. Because SuperContacts are so numerous and so tiny (i.e. they not only thin, they are short) a spare circuit is never very far away. It may even be on the die above or below the offending die. It might even be a few die above or below. That ends up being up to the chip architect. But the capability is part if our suite of Di3D technologies.
Sounds complicated, right? It is. Being able to marshal a massive number of spares for very fine-grained repairs turns the test and repair job into a massive job. So there is one more trick in our bag. Built-in Test and Repair. BiSTAR does not depend on external test equipment. Each stack has a very small microprocessor installed inside. That processor is programmed to manage the stack, which is to say it runs all the self-test circuits. It tells them what to do, when to do it, collects the results and orders the repairs. And the best part is that it keep doing its job automatically every time the stack powers-up…or more accurately, each time it boots-up. In fact, it can be instructed to go do test and repair any time, not just when power cycles. Even after a Tezzaron Di3D chip is installed in a system sitting on a mountaintop in the middle of nowhere, BiSTAR can keep on making repairs if defects develop.
This is what we mean when we say we use 3D technology to solve 3D problems.
As you can see, it is a circular self-reinforcing process. It is critical to note that breaking any step in the circle would disable every other part of the circle. The first vital step is being willing to bond untested wafers. It is a radical departure from the entire history of conventional IC manufacturing and the single most critical step in the development of a cost effective 3D manufacturing process, Di3D.