3D has been a decade or two or more in development: “ready in 18 months from now” was the mantra of 3D for far too long. We believe we know why. The harsh reality is that 3D just wasn’t necessary. The realities of Moore’s Law saw to that. (Gordon Moore predicted, accurately, that we would double the number of transistors we could fit in a given space every few years, for many years to come. And we have.) The magic of lithographic shrinks to silicon fabrication processes have made most of the forms of innovation the industry could have undertaken simply unnecessary. When foundries can deliver processes that allow IC designers to build devices that are are faster, lower power, and cheaper (per transistor) more quickly and more reliably than any other form of innovation can, who needs 3D?
This doesn’t sound much like a pep talk for the 3D industry, does it.
Little exaggeration is required to assert the greatest engine of advancement in the world for the last 60 years has been the steady improvement in semiconductor products and the systems we have created with them. Nothing is they way it used to be; from farming, to medicine, to heavy equipment, to energy, to a teenager’s first date. Everything has been changed by the relentless arrival of cheaper, faster, lower power transistors. The days when that was not true have almost slipped from living human memory. This is our way of life. Or at least it was.
We can see the coming of new wonders so clearly in front of us that we make movies about them. Intelligent robots, seamless virtual reality, better-than-original prosthesis, and even flying cars are no longer the stuff of silly dreams but a settled certainty in the public mind. The problem is that the rocket ship of semiconductor improvement that so many of us have taken for granted…has started to sputter. The fuel is nearly gone.
There is no doubt that we are going to continue to make semiconductor transistors smaller for a few more years to come. That is not the problem. But there are problems. The traditional realization of Moore’s Law had three key elements: more transistors, cheaper transistors and lower power circuits. The very few largest semiconductor manufacturers in the world are pulling out all the stops to try to build smaller transistors. The problems have more to do with cost and power. And there are a few other problems coming into the mix, just to keep it interesting. But let’s focus on the biggest but perhaps least obvious one, process specialization, and work our way back through the others.
Once upon a time when a new silicon process was developed, it was installed in the fab and it was used to build every type of semiconductor product there was. But one-size-fits-all process development did not last long, most notably with the advent of some specialized processes for building dense and/or non-volatile memory. The number of different process flows that emerged at each lithographic node slowly climbed almost without notice. But today we are faced with a explosion of process options. So why is that a problem? Because except for a very few, very high volume applications, we tend to want to build chips that can do quite a number of very different things and do them very well. We want them to calculate quickly using little power. We want them to interface to the outside world at very high speed, or perhaps tolerate high voltages. We want them to store huge caches of data the processor can reach very quickly and we want vast seas of non-volatile memory at our disposal. Each of those jobs requires a different process optimization. That was OK when we were willing to put each specialized device into its own package. But today we want all that capability in one chip. We want to build Mr. Spock’s Tricorder…the latest one that fits in his pocket; not that clunky one with a shoulder strap he used in the first season of Star Trek in the 60’s.
Let’s cover speed and power next, because if you want to build a Tricorder, those are critical. Today, the single biggest cause of speed and power problems we see in integrated circuits are simplest circuit element we use: wire. Circuit delays and power consumption will continue to explode even if we come up with transistors that consume zero power and switch infinitely quickly, simply because wires are getting longer. Why? Because although we have been able to get twice as many transistors into the same space with each process shrink, we have been putting more than twice as many transistors into each next generation chip. As a result, die themselves have continuously gotten bigger. Lots bigger. So the wires that cross the die are getting lots longer. Electricity may fly down a wire at almost the speed of light, but at the speeds we operate chips today, on-die wire length makes a big difference. And the power it takes to push a signal through that wire is significant too; made more so by the staggering number of wires involved. The upshot is that shrinking transistors do not have a direct impact on these problems. Making the transistors smaller may allow us to pack more of them closer to each other so that we do not need to run a wire as far to get around them, but we invariably add more transistors (to provide more fancy features and functions) so that the wires get even longer. Wiring is now the dominant contributor the delays and power consumption on modern ICs. Building ICs out of superconductors may solve this problem someday, but not in the next 20 years. And we need to continue to make progress now.
In the end, all of this comes down to cost. Even if we can fix the transistor size problem and the power problem and the speed problem, if costs do not fit customer expectations, it is all for nothing. But cost is a complicated thing. In manufacturing, there are at least four very critical kinds of costs to be considered. The first is the cost of the factory and the development of the process used in that factory. That money has got to come from somewhere. Perhaps from local government but more often from customers as part of the selling price of the item being made. The next group of costs include all the money needed to develop the particular item being built. Some of those costs may be called “R&D” and others may be called “NRE” (non-recurring engineering charges) but again, the money has got to come from somewhere. This time it is even more likely to come out of the customer’s pocket. Next there are the costs directly related to building the item itself; the raw materials. the electricity to run the machines, the wages of the workers, etc.. And finally there are all the costs of running the business, including selling the product and servicing the customers. The interesting thing about most of these costs is that many of the items that contribute to them can be made more efficient with larger unit volume.
This is all very elementary but very important to keep in mind when considering the cost challenges we face in semiconductor today. The rate of cost increases for building factories and developing processes are both well documented and staggering. But with high enough product volume, we may be able to convince ourselves it will all come out fine for a little while longer. But we may not. There is a spirited debate underway on that topic, with lots of evidence on hand that those costs, when viewed on a per transistor basis, started going the wrong way several process nodes ago. But what is absolutely indisputable is the fact that the costs of product development have gone into the stratosphere as well, and continue to rise at an alarming pace.
Even if we just look at the price of the mask set needed to build a product, it is easy to see that the vast majority of the traditional semiconductor industry simply cannot afford to move on to more aggressive lithographic nodes. A few of the big players who build the very highest volume die in the world, invariably for the consumer market, may be able to amortize development costs associated with more aggressive process nodes, but the rest of the market, notably the high performance market, needs a different solution.
There is another reason we think 3D has crawled out of the primordial mud of development at such a slow pace. Mostly it has been and is being done the wrong way. Across the industry most of the “3D” work has been the development of a better packaging technique; a way to interconnect otherwise ordinary 2D integrated circuits in a more compact way. It is an approach that yields some benefits. Unfortunately an approach that produces “some benefits” in the face of an apocalyptic end to technology rocket we have ridden for the last 60 years just isn’t going to cut it. The industry needs a way to get back on track, adding more transistors in less area, at lower cost and lower power. We need to implement transistor-level solutions.
Tezzaron’s Di3D™ (Dis-Integrated 3D™) technology is a direct attack on the the most fundamental problems we face as an industry; transistor density, interconnect power, Interconnect delay and cost. We believe Di3D can be used to continue to drive forward on performance and value for both silicon foundries, product developers and customers. Keep reading if you want to know more about how are bringing this promises into reality.