The Tezzblog

It’s Official – Lithographic Shrinks Will End

…by 2021, according to the authoritative report on the subject, sponsored by the Semiconductor Industry Association (SIA). The report, published each year for the last quarter century, is the 2015 International Technology Roadmap for Semiconductors (ITRS); released July 16, 2016. For the first time ever the report forecasts that the shrink trend line will go flat…and forecasts that it will do so by 2021. Given the indisputable fact that transistor shrinks have been, by a wide margin, the most powerful engine of advancement in our modern technology-rich world, it is akin to announcing that starting in 2021, on a world wide basis, formal education will be terminated at Third Grade level. Nobody will die right away, but the advancements we had taken for granted are suddenly going to be much more difficult to come by.

The good news (for the world) is that this is not actually a sudden development or a surprise. We have all seen it coming. Some have put their head in the sand. Others, like Tezzaron, have been developing alternate technologies that will allow us not only to adapt but to thrive. Interestingly (to me at least) the new ITRS report comes to the same conclusion that I have advocated for 20 years*, namely that the real solution is for us to convert from the mechanistic computing approach we have undertaken since Babbage, and move to an organic approach to computing that emulates the human brain. But like anyone with half a lick of sense, it also acknowledges that we are years away from that new approach yielding systems that can address the massive needs that already exist, much less intercept the still greater needs that will exist by the time the technology matures. Then, rightly, the report pivots to more near term solutions, specifically, 3D and variations on the 3D theme, as the bridge technology we need to tide us over until we can get to a genuinely new paradigm.

Folks who have been following Tezzaron closely have heard this before, but it bears repeating on this occasion. Although the world has seen “the wall” coming for some time and many have seen 3D as the solution, nobody has taken the path Tezzaron has laid out. As loudly as the the ITRS praises 3D as the way forward, not even the ITRS mentions the Tezzaron approach as one of the solutions in front of us. In some sense that is not surprising. The report describes some seemingly obvious 3D projects, such as 3D integration of processors and memory, as having never been done…while Tezzaron, with processor design partners, has already done them and published the results in respected journals. Clearly the editors of the ITRS are not perfectly informed, or are being intentionally obtuse. Be that as it may, the clear focus of the industry has been on 3D packaging technology and that is worlds away from Tezzaron’s accomplishments and our trajectory. Tezzaron is focused on transistor-level 3D. Tezzaron is uniquely focused on finding a way to continue doing what the semiconductor industry has been doing since 1947…packing more high performance transistors into less area at lower power levels.

Do not be confused. “Going vertical” is not new in the semiconductor world. The advent of pillar and trench DRAM bit cell structures are a great example of Z-axis innovation in modern semiconductors. And 3D NAND, if you are willing to include brutally slow memory options on the list, are another. And on a similar brutally slow memory bender, we can include the 3D-XPoint work that was announced last year. But none of those actually increase the density of “real” transistors (the sort you would need to build a microprocessor or an FPGA) on one piece of silicon. Those technologies are specifically designed to make discrete charge storage more compact. They do not allow the construction of more complex high performance circuits at lower power. But let’s acknowledge that their inventors are on the right track. Seventy years of focus on two dimensions is probably enough. It is time to look up. And to the credit if the ITRS editors, this edition of the ITRS talks hopefully (perhaps wishfully) about new vertical transistor structures being possible and needed.

8layerTezzaron is all about The Z Path Forward™ and, as everyone can re-read in last year’s press release, has already demonstrated packing more high performance CMOS transistors into less area than any other vendor or research lab in history…and more metal interconnect layers as well. So lithographic shrinks may well be over. But at Tezzaron, increasing high performance transistor density, the core of Moore’s Law, is alive and well…in a whole new way.

 

*This is what happens when you take a Psychology degree before getting an Engineering degree.