Built-in Self Test And Repair

Bi‑STAR® is  Tezzaron’s patented technology for programmable semi-autonomous on-chip testing and repair. Although BIST (Built-in Self-Test) is commonly practiced in the industry, Bi-STAR takes matters one step farther by adding repairs to the effort.

While it must be admitted that doing repairs may not, on it’s face, sound like earth-shattering innovation, it is when Bi-STAR is practiced in the context of Di3D. That is when the real power of the technology becomes apparent.

The fundamental contribution of Di3D is extremely dense vertical interconnect. Di3D and the use of Tezzaron’s SuperContacts make it far more worthwhile to invest in BIST than is normally the case in 2D IC design and it makes effective post-assembly and indeed even in-the-field repairs feasible. That is the power of Bi-STAR.

With Di3D, spares can be made available at very high granularity. No longer must a chip architect settle for swapping in impractically large blocks of circuitry. With Di3D, spares can be managed on a gate level granularity. Spare circuits needed on one die can be invoked from a die several layers above or below the failing circuit, with a negligible impact on circuit performance. Bi-STAR, when practiced in the context of Di3D, addresses the most fundamental issue that has plagued and delayed the emergence of 3D technology in the industry; “The Yield Problem”.



Solving The Yield Problem

The usual way of building ICs is to fabricate the wafer, and then with rather expensive test equipment, probe test the wafer with a very basic test designed to find badly defective die. In some cases, particularly in memory manufacturing, that test equipment may also be used to invoke some basic spares in order to make repairs, and then test the die again. At that point the die will either be passed along to the next packaging step or marked to be thrown away. Generally, at some later time, each of the die passed to the next stage of packaging ends up getting a more aggressive test (which often can only be run on the device after it is in packaged form) whereupon some of the die that had been deemed “not dead” or perhaps even “pretty good”, end up not making the grade and are also resigned to the trash heap. It is the difference between the number of die that make it out of probe and the ones that ultimately pass final test that are the source of the 3D “yield problem”.

Imagine that you are stacking die and doing so with the full knowledge that 10% of them are unlikely to prove good in the end. A 90% final test yield is not a fanciful number. Lots of produce engineers would be happy to be getting that probe yield on their 2D design. Now when two of those die are stacked in a permanent way, the chances that your two die stack will make it through final test has dropped to 81% (90% x 90% is 81%). If a third die is added probable yield drops to 73% and at four die, the chance of success has fallen to 66%. That is pretty discouraging to anyone wanting to do 3D. But these calculations presume that the repairs that were needed had already been done before stacking. They also presume that the stacking operation does nothing to make the die in question “more repairable”. That is where Di3D and Bi-STAR come into play.

The wafers and the die fabricated for a Di3D product will not fare any better in an ordinary probe test than any other wafers. There is no magic there. There may be local spares on each of the die on that Di3D wafer that can be successfully invoked to fix a problem, but there is no reason to do so before stacking because Di3D employs wafer stacking, not die stacking. Even if there are totally dead die on the wafer, they are still going to get bonded to another die on an adjacent wafer. In fact, it is not until the wafer stack is completed that there is any reason to invoke a functional test on any of the die. They are all getting bonded, working or not.

Conventional thinking would suggest we should expect disastrous yields from wafer bonding, but that all changes when Di3D and Bi-STAR are in play. With Di3D, a spare can come from an adjacent wafer which may be as little as 20 microns away, directly above or below the faulty circuit. The chances are good that even if the spare was several wafers away, say 60 microns or 100 microns away, the impact to circuit performance for picking one of those spares would be negligible. What that means in practical terms is that Di3D converts stacking from a 3D yield “problem” into a yield booster. Now when die are added to the stack, spares are added to the stack; usable spares. The stack becomes MORE reparable and yield can go up, rather than down, when more die are added to the stack.

Granted, the availability of spares must be designed into any device implemented with Di3D techniques, but it is Di3D that makes the use of those spares possible.

Booting-up a Di3D Chip

Bi-STAR is not practiced in production using expensive external test equipment. Bi-STAR technology puts a small microprocessor inside every Di3D stack…at least one per finished chip stack.

At power-up Bi‑STAR, under internal processor control, tests the entire chip. The tests can be set to evaluate virtually any circuit in the stack. Running in a massively parallel fashion, Bi-STAR testing can take full advantage of the huge internal bandwidth provided by our SuperContact® vertical interconnect structures. With a “comparator per line” technique, hundreds of thousands of nodes can be evaluated at a time. After testing, the Bi-STAR processor uses a flexible remapping scheme to invoke spares and repair errors. Bi-STAR test and repair is fast. In Tezzaron’s DiRAM4, for example, more than 256 different different hardware tests can be underway at the same time. With that kind of parallelism test times run into tens of milliseconds, not tens of minutes.

Exactly how Bi-STAR is implemented varies with the sorts of circuits being evaluated. Testing embedded memory functions is different from testing logic functions, but they all come down to using the built-in processor and a little Tezzaron magic to stimulate the circuits under test, and then collect and ultimately act upon the results. Although it might not be absolutely necessary, Tezzaron anticipates that all Di3D products will employ Bi-STAR, and will be designed to boot the internal processor at power-up to invoke the latest repair map. We anticipate that in environments with a particularly high bar set for reliability, the device will likely be programmed to monitor and flag any new additions to the repair map, just to get an early warning that things might be going badly. Some designs may even want to pause execution and go run a scrub on a Di3D device to correct any soft errors, just to stay ahead of the game. The point is that because of the programmable nature of Bi-STAR, lots of options are available.

Bi-STAR Benefits

  • Eliminates external test equipment – all tests are done on-board
  • Reduces test time – tests use internal bandwidth and can be highly parallel.
  • Improves yield – conventional chips can handle fewer than 100 hard fails; chips with Bi‑STAR correct thousands
  • Optional error and condition reporting
  • Continuous “soft” error checking and correction feasible in some applications
  • In-the-field “hard” error detection and repair
  • Architectural flexibility can be applied in varying forms in response to specific device and market needs.