Bi‑STAR® is Tezzaron’s patented technology for on-chip testing and repair of memory. It reduces manufacturing cost, increases yield, and vastly improves the reliability of memory chips.
Bi‑STAR consists of a processor, software, and support circuitry, all embedded on a memory chip. These elements test and repair the chip at power-up and then monitor, test, and repair the chip “on-the-fly” during normal use. The silicon area overhead for Bi‑STAR is less than one square millimeter in a 0.13 micron process; very much less at smaller nodes.
At power-up Bi‑STAR tests the entire memory chip – every line driver, secondary bus driver, CAM, and sense amplifier. Word lines and bit lines are tested for shorts; bit capacitors are checked for leaks. The tests can be set to generate and compare virtually any memory patterns in virtually any address sequences. Running in a massively parallel fashion, Bi-STAR testing takes full advantage of the chip’s internal bus bandwidth with a “comparator per bit line” technique. A one-Gigabit implementation can test 300,000 bits per access, pipelined at 5 nanosecond cycles.
After testing, the chip’s processor uses a flexible remapping scheme to repair any errors. The processor views all of memory as a collection of bits, performing logical-to-physical CAM mapping on every access. The memory bits are organized into two areas: a memory block of the appropriate size and a pool of redundant bits. Faulty bits are mapped out and replaced with good bits from the redundant bit pool. Bi‑STAR’s flexible mapping scheme allows remapping by row, by column, by sub-array, and by individual bits. Bi‑STAR determines the best repair option for each faulty area detected. Sub-array replacement is the most comprehensive option, mapping out an entire section of the memory system including drivers, sense amplifiers, and local decode and mapping structures.
Assuming 400 different test patterns on a 1-Gigabit chip, Bi-STAR can finish the testing and remapping in only 32 milliseconds.
Random errors (bit flips) can happen in any memory chip – generally caused by background radiation. Bi‑STAR continuously seeks out and deals with these errors. During normal use the embedded microprocessor runs in the background, “scrubbing” the chip to detect and correct any new errors. For a 1-Gigabit chip, complete memory scrubbing occurs every 2 minutes.
Bi‑STAR tracks the occurrence and location of errors. If a bit experiences frequent errors, Bi‑STAR flags it as unreliable and schedules a repair. Repair is done on-the-fly during the next refresh cycle, remapping the flagged bit with a replacement from the redundant bit pool. If a larger area is flagged, remapping occurs at the next power-up.
Scrubbing, error detection/correction, and repair are performed on-chip without using system resources. Bi‑STAR functions do not interfere with normal memory access and are completely transparent to the rest of the system.
Bi‑STAR can be configured to report errors and conditions. In critical applications or harsh environments, this feature allows failing parts to be detected and replaced before Bi‑STAR exhausts its pool of redundant bits. Bi‑STAR reporting can use any of several formats, including SMBus-compliant formats, and can be enabled during power-on testing and/or during normal operation.
Redundant memory areas are common to all memory chips but remapping is usually performed in a coarse-grained manner, perhaps four rows or columns at a time. This means that on a typical memory chip, a single bad bit consumes a large amount of redundant memory; a mere handful of widely separated bad bits can exhaust the redundant memory area and render the chip useless. Some chips allow finer remapping, using single rows or columns, but only Bi‑STAR’s flexible fine-grained remapping can replace individual bits as well as rows, columns, or sub-arrays. The result is a much more efficient use of redundant bits.
Virtually all memory chips require expensive external test equipment that is connected to the chip with manual probe-testing. Testing speed is limited by the bandwidth of the connection. Bi‑STAR eliminates the cost of the equipment and the time and skill required for manual probing; it also reduces the time spent in actual testing by several orders of magnitude.
Most memory chips are tested for repair and remap only once, on the production line. If a bit becomes “stuck” at a later time (due to magnetism, radiation, heat, impact, or other damage) it cannot be repaired; the entire chip must be replaced. With Bi‑STAR, these “hard” errors are detected and remapped within minutes.
A few state-of the-art memory chips include on-board processors for hard error testing and repair/remapping. These processors perform coarse-grained repairs at the factory or at power-up. At present, only Bi‑STAR performs fine-grained remapping and only Bi‑STAR repairs hard errors on-the-fly.
Memory devices without Bi‑STAR ignore the random, recoverable bit-flips caused by radiation; if a bit is flipped, the error remains until a new value is written to that location. Some processor chipsets use ECC (error checking and correction) or EDAC (error detection and correction) to detect and correct these “soft” errors in their memory banks, but this adds significant complexity and cost. Bi‑STAR’s on-board memory scrubbing performs this function without using any system resources. It runs faster than system-level ECC/EDAC by several orders of magnitude.
Because it continually monitors chip performance, Bi‑STAR can detect and report unreliable behavior long before the chip actually fails. No other memory system provides an on-chip reporting feature.
For the manufacturer, Bi‑STAR reduces costs in several ways:
For the end user, Bi‑STAR offers unparalleled reliability:
Tezzaron may implement Bi‑STAR’s powerful suite of test and repair capabilities in varying forms on future memory chips in response to specific market needs.