Our Technology for Non-Technical Folks

The Tezzaron® Story in Simple Terms

If you’re not already a semiconductor guru, our technology might seem like one more bit of gobbledygook in a sea of technical black magic. But it’s a fascinating story, and we think it’s worth explaining! So here’s the Tezzaron® story in simple terms:

Making Chips – the back story

Computer chips have been made exactly the same way for over 40 years. You start with a blank slice of silicon. You put down gossamer-thin layers of patterned metal and glass. Repeating this process in various ways creates transistors – lots of transistors – and tiny wires between them. Transistors and wires; that’s really all it takes to produce memory devices, microprocessors, amplifiers, and all those other chips inside your electronic gadgets.

A computer circuit board with chipsA computer circuit board with chips

On the inside, each chip’s transistors and wires make up a single “integrated circuit” or IC.

Integrated circuits aren’t made one at a time; they’re made in big batches on circular silicon “wafers.” Each wafer is actually a single crystal of silicon, but that’s another story. Suffice it to say that dozens, hundreds, even thousands of integrated circuits are patterned on each wafer.

One wafer patterned with many integrated circuitsOne wafer patterned with many integrated circuits

The wafer is cut up – “diced” – into individual integrated circuits. The rectangle of silicon containing one integrated circuit is called a “die” — or, alternatively, a “chip.”

A die with one integrated circuitA die (chip) with one integrated circuit

Each die is then packaged to protect the fragile silicon. The outside of the package is studded with metal connectors – pins or bumps – that let the die communicate with the rest of the world.

Two different chips, one packaged with pins and one with bumps Two different chips, one packaged with pins and one with bumps

Testing Chips

When all is said and done, some chips just don’t come out right. Silicon wafers often have subtle flaws that wreak havoc with the transistors. There’s also the chance of errors during processing, or microscopic bits of dust, or impurities in the materials.

Before the wafer is even diced it generally undergoes “probe testing” to see which dies are good and which are bad (see the picture at the top of this article). Bad dies are marked and discarded after dicing. However, the probe test can’t fully exercise all the functions of the chips; that can only happen after they’re packaged. Then they undergo some seriously tough testing. They’re even loaded into ovens and cooked!

A furnace used for chip burn-in A furnace used for chip burn-in

Only the strong survive this “burn-in.” The survivors go on to final test; they are connected to computers that thoroughly analyze their performance. The chips that fail are repaired or discarded; those that pass all the tests are sold to customers.

Making 3D Chips

As technology has advanced over the years, the transistors and wires have gotten smaller and smaller. More and more stuff has been crammed onto each chip. That’s why our devices – phones, for example – have gotten so small and powerful. In today’s tiniest circuits, each transistor is about the size of a cold virus! It is tremendously difficult (and expensive) to make them any smaller.

Instead of making the transistors smaller, another way to get more of them into each chip is to stack several layers of circuitry into a package. These stacked circuits are called “3D-ICs” (three-dimensional integrated circuits).

There are many interesting ways to stack 3D-ICs, but they all have some things in common:

1 Physical Stacking

You can stack dies on dies, dies on wafers, wafers on wafers, or a combination of these. You can put the layers together using adhesives, or melted metal, or covalent silicon bonds, or whatever works for you. You can stack two layers, or three, or eighteen, or however many you need to get the job done. But you need to stack something.

2 Thinning

A silicon wafer starts out thinner than a dime, but you can’t stack a bunch of dimes and expect them to fit into a chip package. Somewhere along the line, the layers have to get thinner. You can thin a wafer before or after dicing; you can thin a die before or after stacking; but however you do it, you have to end up with a slim stack of circuits.

3 Vertical Interconnections

The layers of the stack need to communicate with one another electronically. They need some vertical wires – along the outside of the stack, or through the whole stack, or just between pairs of layers; a few big fat wires or a vast forest of tiny wires; one way or another, the circuits need to pass signals up and down. You can build wires into each layer before stacking, or drill holes for them after stacking; you can make them out of copper, aluminum, tungsten, polysilicon – any material that conducts electricity.

4 Testing

This is the really tricky part. One bad circuit can ruin the whole stack. Because the layers can’t be fully tested until they’re in a package, there is no way to know ahead of time whether all of them are good. The more layers in each stack, the higher the odds of having a bad one in there. Throwing out a lot of bad chips is expensive! If only a few chips make it through testing, they’re going to be awfully expensive chips. Solving this problem is obviously a high priority.

How Tezzaron® Does It

Tezzaron uses several different stacking methods, but our favorite is wafer-level stacking with hybrid bonding, tungsten interconnects, and built-in self-test and repair. Nobody else is doing it. It is so radically different, most “experts” who first hear about it say “that’s impossible” or “that will never work” – and that is why, so far, only Tezzaron is doing it.

1 Stacking

Tezzaron stacks complete wafers, before they are cut into individual dies. That’s wafer-level stacking. We don’t even probe-test the wafers first. It is only after all the wafers are stacked and diced that we do any testing. And we agree, if our chips were designed in a conventional way, almost none of them would be any good. But our 3D stacked chips are not conventional. We have a few little tricks.


First of all, we stack the wafers without any adhesives. We use the silicon itself for the bond and miniscule bits of melted copper for electrical connections. That’s called hybrid bonding. The bond is actually stronger than the silicon itself – you can’t break the bond without breaking the wafers – and the connection is very, very thin.

2 Thinning

At Tezzaron and everywhere else, the way to thin a wafer is to put it on a big flat turntable and grind it down. The circuits are on the face of the wafer, so the wafer is put onto the turntable face down and the blank backside is ground away.


You have to be careful not to grind the wafer too far; when it gets thinner than a playing card it starts to become flimsy and can eventually crumble to dust.

But at Tezzaron we bond two wafers together first, face-to-face, and we put the entire two-wafer stack into the grinder. Because the bond is so strong, we can thin the top wafer until it’s just a film – thinner, even, than some germs. We can do that because the bottom wafer is still at full thickness, and it’s holding everything together. We can then bond another wafer onto the stack, face down, and thin it. And so on.

We bond each wafer before thinning, and the bond is strong enough that we can grind our wafers extraordinarily thin – about 1/10 the thickness of our competitors’ wafers. That’s our first little trick.

3 Vertical Interconnections

We make our vertical wires by drilling holes in the wafer and filling the holes with tungsten. There is a limit to how narrow and how long anyone can make wires like that. With today’s processing techniques, the length can’t be more than about ten times the width. Because Tezzaron’s wafers are so thin, the wires that run vertically through the wafer are quite short. And because they are so short, they can be very skinny.

Five metal layers; one SuperContact Wafer cross-section showing a vertical wire

Our wafers are 1/10 as thick, so our wires are 1/10 as long, and they can therefore be 1/10 as wide. That means we can put in 10 times as many wires … in each direction. The result: we can have about 100 times as many vertical wires through our stack. In fact, our memory chips have hundreds of thousands of vertical connections between each two layers. That’s the next trick.

4 Testing

After Tezzaron finishes stacking the wafers, we dice the multi-wafer stack. Each die already contains a full, untested stack – but it’s no thicker than a normal die.

A two-layer die (with nickel for scale) A two-layer die (with nickel for scale)

The dies are packaged like normal dies, and then they are tested.

Now things begin to get interesting. With so incredibly many vertical wires in our chips, we can do things that would be otherwise simply impossible. The most important thing we can do is built-in self-test and self-repair. Our memory products are designed to test themselves, and even repair themselves, after they’re in the package. In other words, when we have a chip that does not work, or does not work well enough to sell, we can fix it.

Simply put, our memories have spare circuits built into them. We can disconnect any bad circuit and connect a good circuit in its place. The size of those spare circuits matters a lot. Having a multitude of little spares is much better than having fewer, larger spares. Because Tezzaron has so many vertical wires through the chip, we can do extremely fine-grained repair. That means we can repair more defects in each chip. We call our patented built-in self-test and repair technology Bi-STAR®. And that is the big, winning trick.


This is what we mean when we say we use 3D technology to solve 3D problems.


  • Because we bond wafers before thinning, we can grind our wafers ridiculously thin.
  • Because our wafers are so thin, we can use outrageously tiny vertical wires.
  • Because our vertical wires are so tiny, we can put in a vast amount of vertical interconnect.
  • Because we have so much vertical interconnect, we can do excellent post-assembly repair.
  • Because we can do post-assembly repair, we can afford to stack untested whole wafers.
  • Because we bond whole wafers, we can bond the wafers before thinning.

As you can see, it is a circular self-reinforcing process. It is critical to note that breaking any step in the circle would disable every other part of the circle. The first vital step is being willing to bond untested wafers. It is a radical departure from the entire history of conventional IC manufacturing and the single most critical step in the development of a cost effective 3D manufacturing process.

How long will Tezzaron be the only manufacturer willing to bond untested wafers to make memory products? We suspect not too long. But don’t worry about us. We have a few other tricks in our bag to keep our competitive edge.