3D SRAM Project

FaStack® Synchronous Burst SRAM Prototype

This 3D-IC wafer-stacked device was designed as part of Tezzaron’s “Orion” multi-project proof of concept.


  • Configurable single/dual cycle deselect
  • Fast clock and output-enable access times
  • Single +1.8V +0.2V/-0.2V power supply
  • Separate +3.3V +0.3V/-0.3V isolated output buffer supply
  • SNOOZE MODE for reduced-power standby
  • Common data inputs and data outputs
  • BYTE WRITE and/or GLOBAL WRITE operation
  • Three chip enables for simple depth expansion and address pipelining
  • Clock-controlled and registered addresses, data I/Os and control signals
  • Internally self-timed WRITE cycle
  • Burst control pin for interleaved or linear burst
  • Automatic power-down for portable applications
  • Low capacitive bus loading
  • 1 Mb capacity in 32Kx32 format
  • Fully compatible with Micron® Syncburst™ devices

This high-speed, low-power SRAM prototype was designed for an advanced CMOS process and wafer-stacked to create a 2-layer 3D-IC device.  It integrates a 32Kx32 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter.  All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.  Synchronous inputs include all addresses, all data inputs, three chip enables, burst control inputs, byte write enables, and global write.  Asynchronous inputs include the output enable, clock, and snooze enable.  A burst mode pin selects between interleaved and linear burst modes.  The data-out is also asynchronous.  WRITE cycles are from one to four bytes wide, as controlled by the write control inputs.  Burst operation is initiated with the input pins of either the address status processor or the address status controller.  Internal generation of subsequent burst addresses is controlled by the burst advance pin.  Address and write control are registered on-chip to simplify WRITE cycles and allow self-timed WRITE cycles.  Individual byte enables allow individual bytes to be written.  An additional pipelined enable register delays turning off the output buffer for an additional cycle when a deselect is executed; this allows depth expansion without penalizing system performance.  The SRAM was designed to operate from a split +1.8V/+3.3V power supply.  All inputs and outputs are TTL-compatible.